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| INTEGRATED CIRCUITS XA-H3 CMOS 16-bit highly integrated microcontroller Preliminary specification IC28 Data Handbook 1999 Sep 24 Philips Semiconductors Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 DESCRIPTION The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking. By supporting of up to 32 MB of external memory, these devices provide a low-cost solution to embedded applications of any complexity. Features like DMA, memory controller and four advanced UARTs help solve I/O intensive tasks with a minimum of CPU load. The XA-H3 feature set is a subset of the XA-H4 (see Table 1). The XA-H3/H4 devices are members of the Philips XA (eXtended Architecture) family of high performance 16-bit microcontrollers. The XA-H3 and XA-H4 are designed to significantly minimize the need for external components. FEATURES * Large Memory Support (up to 6 MB external) * De-multiplexed Address/Data Bus * Six Programmable Chip Selects - Support for Unified Memory - allows easy user modification of all code - External ISP Flash support for easy code download * Dynamic Bus Timing - each of 6 chip selects has individual programmable bus timing. * 32 Programmable General Purpose I/O Pins * Four UARTs with 230.4 kbps capability * Eight DMA Channels * Dynamic Bus Sizing - each of 6 Chip Selects can be programmed for 8-bit or 16-bit bus. Table 1. XA-H3 and XA-H4 features comparison Feature Maximum External Memory (Harvard Memory Mode) Maximum External Memory (Unified Memory Mode) Memory Controller supports both Harvard and Unified architectures De-multiplexed Address/Data Bus DRAM Controller DMA Channels Dynamic Bus Sizing Dynamic Bus Timing Programmable Chip Selects General Purpose IO Pins Potential Interrupt Pins Interrupts (programmable priority) XA-H3 6 MB 6 MB Yes Yes No 8 Yes Yes 6 33 16 7 Standard SW 4 High Priority SW 13 Hardware Event Counter/Timers Baud Rate Generators1 Serial Ports Maximum Serial Data Rates Match Characters Hardware Autobaud SCP/SPI Bus NOTE: 1. Can be used as additional counters if not needed as BRGs. 2 plus Watchdog 4 4 UARTS asynch to 230.4 kbps (no sync) No No No XA-H4 32 MB (16 MB Code, 16 MB Data) 16 MB Yes Yes Yes 8 Yes Yes 6 33 16 7 Standard SW 4 High Priority SW 13 Hardware Event 2 plus Watchdog 4 4 USARTS asynch to 230.4 kbps sync to 1 Mbps 4 async chars per USART up to 230.4 kbps 1999 Sep 24 2 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 ORDERING INFORMATION ROMless Only H3 = PXAH30KFBE Temperature range C and Package -40 to +85C, 100-Pin Low Profile Quad Flat Package (LQFP) Freq (MHz) 30 Package Drawing Number SOT407-1 NOTE K=30 MHz, F = (-40 to +85), BE = LQFP PIN CONFIGURATION 83 P2.3_ComClk_TRClk3 94 P0.4_TRClk0 95 P0.5_RTClk0 82 P2.2_RTClk3 90 P0.0_BRG0 87 P2.7_BRG3 92 P0.2_CTS0 85 P2.5_CTS3 91 P0.1_RTS0 86 P2.6_RTS3 80 P2.0_RxD3 81 P2.1_TxD3 93 P0.3_CD0 84 P2.4_CD3 78 CD1_Int2 98 GPOut 97 RxD0 96 TxD0 89 VDD 100 P0.7 77 VDD 99 P0.6 88 VSS VSS VDD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS VDD A16 A17 A18 A19 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MOLD MARK MOLD MARK 76 VSS 75 P1.7_BRG2 74 P1.6_RTS2 73 P1.5_CTS2 72 P1.4_CD2 71 P1.3_TRClk2 70 P1.2_RTClk2 69 P1.1_TxD2 68 P1.0_RxD2 67 P3.7_Int1_TRClk1 66 P3.6_TxD1 65 P3.5_RxD1 64 P3.4_CTS1 63 P3.3_Timer1_BRG1 62 VDD 61 XTALOUT 60 XTALIN 59 VSS 58 P3.2_Timer0_ResetOut 57 P3.1_CS5_RTS1 56 P3.0_CS4_RTClk1 55 Reset_In 54 BLE 53 BHE 52 WAIT_Size16 51 OE WE XA-H3 Top View 100 Pin LQFP Part Number: PXAH30KFBE K = 30 MHz, F = -40 to +85C, BE = LQFP pkg LQFP Package = SOT407-1 D11 ClkOut D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D12 D13 D14 D15 CS3 CS2 79 Int0 CS1 VSS VDD VDD VSS CS0 SU01234 1999 Sep 24 3 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 LOGIC SYMBOL XA-H3 VDD Int0 MISC. Int2 CS4 CS5 ResetOut, Timer0 Timer1 UART1 CD1 RTClk1 RTS1 BRG1 CTS1 RxD1 TxD1 TRClk1 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 XTAL2 PORT3 VSS XTAL1 CS3 CS2 CS1 CS0 Int1 UART3 RxD3 TxD3 RTClk3 ComClk, TRClk3 CD3 CTS3 RTS3 BRG3 PORT2 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 A19 - A0 D15 - D0 UART2 RxD2 TxD2 RTClk2 TRClk2 CD2 CTS2 RTS2 BRG2 PORT1 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 ClkOut BHE BLE OE WE UART0 TxD0 RxD0 BRG0 RTS0 CTS0 CD0 TRClk0 RTClk0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 GPOut SU01235 PORT0 Wait, Size16 ResetIn 1999 Sep 24 4 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 XA-H3 BLOCK DIAGRAM XA-H3 CPU Core 256 Bytes Data SRAM Data MMR Bus SFR Bus DMA R0 UART 0 Port 0 DMA T0 Port 1 DMA R1 UART 1 DMA T1 Port 2 DMA R2 Port 3 UART 2 DMA T2 Timer 0 DMA R3 UART 3 DMA T3 Timer 1 Watchdog Timer Memory Bus Controller 6 Chip Selects Dynamic Bus Sizing Dynamic Bus Timing External System Bus SU01247 1999 Sep 24 5 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 XA-H3 MEMORY MAPS FFFFFFh 6 MB * Common Code and Data Space 000000h Unified Memory (von Neuman architecture) *In either memory architecture, the XA-H3 can support a maximum of 6 MB because each of six Chip Selects is capable of 1 MB each. In Unified architecture, Code and Data can share the same physical Memory Chip and address space. Code Space + Data Space = 6 MB Maximum Total with 1 MB per Chip Select. Each CS (and thus, 1 MB space) can support either Code or Data in Harvard architecture. FFFFFFh FFFFFFh Dedicated Code Space Dedicated Data Space 000000h 000000h Harvard Architecture SU01248 1999 Sep 24 6 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 PIN DESCRIPTIONS Mnemonic VSS Lqfp Pin No. 1, 19, 28, 44, 59, 76, 88 2, 20, 29, 43, 62, 77, 89 55 52 60 61 49 48 Type Ground: 0 V reference. I Power Supply: This is the power supply voltage for normal, idle, and power down operation. I Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor to begin execution at the address contained in the reset vector. Wait/Size16: During Reset, this input determines bus size for boot device ("1" = 16-bit boot device; "0" = 8-bit.) During normal operation this is the Wait input ("1" = Wait; "0" = Proceed.) Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits. Crystal 2: Output from the oscillator amplifier. Chip Select 0: This output provides the active low chip select to the boot device (usually ROM or Flash.) From reset, it is enabled and mapped to an address range based at 000000h. It can be remapped by software to a higher base in the address map (see the "Memory Interface" chapter in the XA-H3 User Manual.) Chip Select 1*: Chip Selects 1 through 5 come out of reset disabled. They function as normal chip selects on the H3. CS1 can be "swapped" with CS0 (see the SWAP operation in the "Memory Controller" chapter of the XA-H3 User Manual.) CS1 is usually mapped to be based at 000000h after the swap, but is capable of being based anywhere in the 16 MB address space. Chip Select 2 *: Active low Chip Selects CS1 through CS5 come out of reset disabled. They can be programmed to function as normal chip selects. CS2 through CS5 are not used with the "SWAP" operation (only /CS0 and CS1 can be swapped; see "Memory Controller" chapter in the XA-H3 User Manual.) They are mappable to any region of the 16 MB address space. Chip Select 3 *: See Chip Select 2 for description. Write Enable: Goes active low during all bus write cycles only. Output Enable: Goes active low during all bus read cycles only. Byte Low Enable: Goes active low during all bus cycles that access data bus lines D7 - D0, read or write. Byte High Enable: Goes active low during all bus cycles that access data bus lines D15 - D8, read or write. Never goes active on an 8-bit bus; always goes active on Reads or Fetches on a 16-bit bus, even if the processor does not need these bits. In other words, all Reads (byte or word) on a 16-bit bus, assert BHE. Clock Output: This pin outputs a buffered version of the internal CPU clock. The clock output may be used in conjunction with the external bus to synchronize WAIT state generators, etc. The clock output may be disabled by software. WARNING: The capacitive loading on this output must not exceed 40 pf. Address[19:0]: These address lines output A19 - A0 during all external bus cycles. Data[15:0]: Bi-directional data bus, D15 - D0; for those bus cycles that are programmed to occur on an "8-bit bus", D15 - D8 are unused. P0.0_BRG0*: Port 0 Bit 0, or UART0 BRG output, or UART0 TxClk output P0.1_RTS0: Port 0 Bit 1 , or UART0 RTS (Request To Send) output. P0.2_CTS0: Port 0 Bit 2, or UART0 CTS (Clear To Send) input. P0.3_CD0: Port 0 Bit 3, or UART0 Carrier Detect input. P0.4_TRClk0: Port 0 Bit 4, or UART0 TR clock input. P0.5_RTClk0: Port 0 Bit 5, or UART0 RT clock input. P0.6: Port 0 Bit 6 P0.7: Port 0 Bit 7 TxD0: Transmit data for UART0. 1 1 1 1 1, 2 1, 2 1 1 Name and Function See Note VDD ResetIn WAIT/ Size16 XTALIn XTALOut CS0 CS1 I I I I O O CS2 47 O CS3 WE OE BLE BHE 46 50 51 54 53 O O O O O See Pins 56, 57 for 2 additional Chip Selects ClkOut 45 O A19 - A0 D15 - D0 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 TxD0 24 - 21, 18 - 3 42 - 30, 27 - 25 90 91 92 93 94 95 99 100 96 O I/O I/O I/O I/O I/O I/O I/O I/O I/O O 1999 Sep 24 7 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 Mnemonic RxD0 GPOut Lqfp Pin No. 97 98 Type I O RxD0: Receive data for UART0 Name and Function See Note GPOut - General Purpose Output Bar: Similar to GPIO, but Push/Pull and inverted output only. WARNING: This output is inverted. The polarity of the pin is the opposite of the bit that drives it (GPOut[7]) P1.0_RxD2: Port 1 Bit 0, or UART2 RxD input P1.1_TxD2: Port 1 Bit 1, or UART2 TxD output P1.2_RTClk2: Port 1 Bit 2, or UART2 RT Clock input P1.3_TRClk2: Port 1 Bit 3, or UART2 TR Clock input P1.4_CD2: Port 1 Bit 4, or UART2 Carrier Detect input P1.5_CTS2: Port 1 Bit 5, or UART2 Clear To Send input P1.6_RTS2: Port 1 Bit 6, or UART2 Request To Send output P1.7_BRG2: Port 1 Bit 7, or BRG output, or TxClk output (see UART clk diagrams in the XA-H3 User Manual.) P2.0_RxD3: Port 2 Bit 0, or UART3 Rx Data input P2.1_TxD3: Port 2 Bit 1, or UART3 Tx Data output P2.2_RTClk3: Port 2 Bit 2, or UART3 RT Clock input P2.3_ComClk_TRClk3: Port 2 Bit 3, or UART3 TR Clock input P2.4_CD3: Port 2 Bit 4, or UART3 Carrier Detect input P2.5_CTS3: Port 2 Bit 5, or UART3 Clear To Send input P2.6_RTS3: Port 2 Bit 6, or UART3 Request To Send output P2.7_BRG3: Port 2 Bit 7, or BRG output, or TxClk output (see UART clock diagrams in the XA-H3 User Manual.) P3.0_CS4_RTClk1: Port 3 Bit 0, or CS4 output, or UART1 RT Clock input Active low chip selects CS1 through CS5 come out of reset disabled. CS2 through CS5 are not used with the "SWAP" operation (see "Memory Controller" chapter in the XA-H3 User Manual.) They are mappable to any region of the 16 MB address space. P3.1_CS5_RTS1: Port 3 Bit 1, or CS5 output, or UART1 Request To Send output Active low chip selects CS1 through CS5 come out of reset disabled. CS2 through CS5 are not used with the "SWAP" operation (see "Memory Controller" chapter in the XA-H3 User Manual.) They are mappable to any region of the 16 MB address space. P3.2_Timer0_ResetOut: Port 3 Bit 2, or Timer0 input or output, or ResetOut output. ResetOut: If the ResetOut function is selected, this pin outputs a low whenever the XA-H3 processor is reset by an internal source (Watchdog Reset or the RESET instruction.) WARNING: Unlike the other 31 GPIO pins, during power up reset, this pin can output a strongly driven low pulse. The duration of this low pulse ranges from 0 ns to 258 system clocks, starting at the time that VCC is valid. The state of the ResetIn pin does not affect this pulse; in other words ResetIn is not passed to ResetOut. When used as GPIO, this pin can also be driven low by software without resetting the XA-H3. P3.3_Timer1_BRG1: Port 3 Bit 3, or Timer1 input or output, or UART1 BRG output. P3.4_CTS1: Port 3 Bit 4, or UART1 Clear To Send input P3.5_RxD1: Port 3 Bit 5, or UART1 Receive Data input P3.6_TxD1: Port 3 Bit 6, or UART1 Transmit Data output P3.7_Int1_TRClk1: Port 3 Bit 7, or External Interrupt 1 input, or UART1 TR Clock input CD1_Int2: UART1 Carrier Detect, or External Interrupt 2 External Interrupt 0 2 2 2 2 2 2 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 68 69 70 71 72 73 74 75 80 81 82 83 84 85 86 87 56 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P3.1 57 I/O P3.2 58 I/O P3.3 P3.4 P3.5 P3.6 P3.7 CD1_Int2 Int0 63 64 65 66 67 78 79 I/O I/O I/O I/O I/O I/O I/O NOTES: 1. See XA-H3 User Guide, "Pins Chapter," for how to program selection of pin functions. 2. RTClk input is usually used for Rx Clock if an external clock is needed, but can be used for either Rx or Tx or both. TRClk is usually used for Tx Clock, but can be used for Rx or Tx or both. 1999 Sep 24 8 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 CONTROL REGISTER OVERVIEW There are two types of control registers in the XA-H3, these are SFRs (Special Function Registers), and MMRs (Memory Mapped Registers.) The SFR registers, with the exception of MRBL, MRBH, MICFG, BCR, BRTH, BRTL, and RSTSRC are the standard XA core registers. See WARNINGs about BCR, BRTH, and BRTL in Table 2. SFRs are accessed by "direct addressing" only (see IC25 XA User Manual for direct addressing.) The MMRs are specific to the XA-H3 on-chip peripherals, and can be accessed by any addressing mode that can be used for off-chip data accesses. The MMRs are implemented in a relocatable block. See the "Memory Controller" chapter in the XA-H3 User Manual for details on how to relocate the MMRs by writing a new base address into the MRBL and MRBH (MMR Base Low and High) registers. Table 2. Special Function Registers (SFR) Name BCR Description Bus Configuration Reg RESERVED - see Warning BTRH BTRL MRBL# MRBH# MICFG# Bus Timing Reg High Bus Timing Reg Low MMR Base Address Low MMR Base Address High ClkOut Tri-St Enable 1 = Enabled Code Segment Data Segment Extra Segment 469h 468h 496h 497h 499h SFR Address 46Ah Bit Functions and Addresses MSB LSB WARNING - Never write to the BCR register in the XA-H3 - it is initialized to 07h, the only legal value. This is not the same as for some other XA derivatives. WARNING - Immediately after reset, always write BTRH = 51h, followed by writing BTRL = 40h in that order Follow these two writes with five NOPS. This is order. NOPS not the same as for some other XA derivatives. MA15 MA23 - MA14 MA22 - MA13 MA21 - MA12 MA20 - - MA19 - - MA18 - - MA17 - MRBE MA16 CLKOE Reset Value 07h FFh EFh x0h xx 01h CS DS ES 443h 441h 442h 00h 00h 00h 33F IEH* Interrupt Enable High 427h EHSWR3 33E EHSWR2 33D EHSWR1 33C EHSWR0 33B - 33A EAuto 339 ESC23 338 ESC01 00h 337 IEL* IPA0 IPA1 IPA2 IPA3 IPA4 IPA5 IPA6 IPA7 Interrupt Enable Low Interrupt Priority A0 Interrupt Priority A1 Interrupt Priority A2 Interrupt Priority A3 Interrupt Priority A4 Interrupt Priority A5 Interrupt Priority A6 Interrupt Priority A7 426h 4A0h 4A1h 4A2h 4A3h 4A4h 4A5h 4A6h 4A7h - - - - EA - - - 336 EDMAH 335 EDMAL PT0 PT1 PDMAL 334 EX2 333 ET1 - - - - - - - - 332 EX1 331 ET0 PX0 PX1 PX2 PDMAH PSC01 PAutoB PHSWR0 PHSWR2 330 EX0 00h 00h 00h 00h 00h 00h 00h 00h 00h Reserved PSC23 - PHSWR1 PHSWR3 387 P0* P1* P2* P3* Port 0 Port 1 Port 2 Port 3 430h 38F 431h 397 432h 39F 433h 386 38E 396 39E 385 38D 395 39D 384 38C 394 39C 383 38B 393 39B 382 38A 392 39A 381 389 391 399 380 FFh 388 FFh 390 FFh 398 FFh 1999 Sep 24 9 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 Name Description SFR Address Bit Functions and Addresses MSB LSB Reset Value P0CFGA P1CFGA P2CFGA P3CFGA P0CFGB P1CFGB P2CFGB P3CFGB Port 0 Configuration A Port 1 Configuration A Port 2 Configuration A Port 3 Configuration A Port 0 Configuration B Port 1 Configuration B Port 2 Configuration B Port 3 Configuration B 470h 471h 472h 473h 4F0h 4F1h 4F2h 4F3h 5 5 5 5 5 5 5 5 227 PCON* Power Control Reg 404h - 20F PSWH* PSWL* PSW51* RSTSRC RTH0 RTH1 RTL0 RTL1 SCR Program Status Word High Program Status Word Low 80C51 Compatible PSW Reset Source Reg Timer 0 Reload High Timer 1 Reload High Timer 0 Reload Low Timer 1 Reload Low System Configuration Reg 401h 400h 402h 463h 455h 457h 454h 456h 440h - SM 207 C 217 C ROEN 226 - 20E TM 206 AC 216 AC - 225 - 20D RS1 205 - 215 F0 - 224 - 20C RS0 204 - 214 RS1 - 223 - 20B IM3 203 - 213 RS0 - 222 - 20A IM2 202 V 212 V R_WD 221 PD 209 IM1 201 N 211 F1 R_CMD 220 IDL 208 IM0 200 Z 210 P R_EXT 3 7 00h 00h 00h 00h 2 2 00h - - - PT1 PT0 CM PZ 00h 21F SSEL* SWE Segment Selection Reg Software Interrupt Enable 403h 47Ah ESWEN - 21E R6SEG SWE7 21D R5SEG SWE6 21C R4SEG SWE5 21B R3SEG SWE4 21A R2SEG SWE3 219 R1SEG SWE2 218 R0SEG SWE1 00h 00h 357 SWR* 42Ah - 356 SWR7 355 SWR6 354 SWR5 353 SWR4 352 SWR3 351 SWR2 350 SWR1 00h 287 TCON* TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Timer 0 High Timer 1 High Timer 0 Low Timer 1 Low Timer 0/1 Mode 410h 451h 453h 450h 452h 45Ch GATE TF1 286 TR1 285 TF0 284 TR0 283 IE1 282 IT1 281 IE0 280 IT0 00h 00h 00h 00h 00h C/T M1 M0 GATE C/T M1 M0 00h 1999 Sep 24 10 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 Name Description SFR Address Bit Functions and Addresses MSB LSB Reset Value 28F TSTAT* Timer 0/1 Extended Status 411h - 2FF WDCON* WDL WFEED1 WFEED2 Watchdog Control Watchdog Timer Reload Watchdog Feed 1 Watchdog Feed 2 41Fh 45Fh 45Dh 45Eh PRE2 28E - 2FE PRE1 28D - 2FD PRE0 28C - 2FC - 28B - 2FB - 28A T1OE 2FA WDRUN 289 - 2F9 WDTOF 288 T0OE 2F8 - 6 00h x x 00h NOTES: * SFRs marked with an asterisk (*) are bit addressable. # SFRs marked with a pound sign (#) are additional SFR registers specific to the XA-H3 and XA-H4. 1. The XA-H3 implements an 8-bit SFR bus, as stated in Chapter 8 of the IC25 Data Handbook XA User Guide. All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. 16-bit SFR reads will return undefined data in the upper byte. 2. SFR is loaded from the reset vector. 3. F1, F0, and P reset to "0". All other bits are loaded from the reset vector. 4. Unimplemented bits in SFRs are "X" (unknown) at all times. "1"s should not be written to these bits since they may be used for other purposes in future XA derivatives. The reset value shown for these bits is "0". 5. Port configurations default to quasi-bidirectional when the XA begins execution after reset. Thus all PnCFGA registers will contain FFh and PnCFGB register will contain 00h. See warning in XA-H3 User Manual about P3.2_Timer0_ResetOut pin during first 258 clocks after power up. Basically, during this period, this pin may output a strongly-driven low pulse. If the pulse does occur, it will terminate in a transition to high at a time no later than the 259th system clock after valid VCC power up. 6. The WDCON reset value is E6 for a Watchdog reset; E4 for all other reset causes. 7. The RSTSRC register reflects the cause of the last XA reset. One bit will be set to "1", the others will be "0". RSTSRC[7] enables the ResetOut function; "1" = Enabled, "0" = Disabled. See XA-H3 User Manual for details; RSTSRC[7] differs in function from most other XA derivatives. 8. The XA guards writes to certain bits (typically interrupt flags) that may be written by a peripheral function. This prevents loss of an interrupt or other status if a bit was written directly by a peripheral action between the read and write of an instruction that performs a read-modify-write operation. XA-H3 SFR bits that are guarded in this manner are: TF1, TF0, IE1, and IE0 (in TCON), and WDTOF (in WDCON). 1999 Sep 24 11 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 Table 3. Memory Mapped Registers (MMR) MMR Name Read/Write or Read Only Size Address Offset Description Reset Value UART0 Registers UART0 Write Register 0 UART0 Write Register 1 UART0 Write Register 2 UART0 Write Register 3 UART0 Write Register 4 UART0 Write Register 5 Reserved - do not write Reserved - do not write UART0 Write Register 8 UART0 Write Register 9 UART0 Write Register 10 UART0 Write Register 11 UART0 Write Register 12 UART0 Write Register 13 UART0 Write Register 14 UART0 Write Register 15 Reserved - do not write Reserved - do not write UART0 Read Register 0 UART0 Read Register 1 Reserved - do not write UART0 Read Register 3 Reserved - do not write Reserved - do not write UART0 Read Register 8 Reserved - do not write UART0 Read Register 10 Reserved - do not write RO 8 RO RO 8 8 8 8 RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 800h 802h 804h 806h 808h 80Ah 80Ch 80Eh 810h 812h 814h 816h 818h 81Ah 81Ch 81Eh 828h 82Ah 820h 822h 824h 826h 82Ch 82Eh 830h 832h 834h 836-83Eh UART1 Registers UART1 Write Register 0 UART1 Write Register 1 UART1 Write Register 2 UART1 Write Register 3 UART1 Write Register 4 UART1 Write Register 5 Reserved - do not write Reserved - do not write UART1 Write Register 8 UART1 Write Register 9 UART1 Write Register 10 UART1 Write Register 11 UART1 Write Register 12 UART1 Write Register 13 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 12 840h 842h 844h 846h 848h 84Ah 84Ch 84Eh 850h 852h 854h 856h 858h 85Ah Command register Tx/Rx Interrupt & data transfer mode Extended Features Control Receive Parameter and Control Tx/Rx miscellaneous parameters & mode Tx. parameter and control Reserved - do not write Reserved - do not write Transmit Data Buffer Master Interrupt control Miscellaneous Tx/Rx control register Clock Mode Control Lower Byte of Baud rate time constant Upper Byte of Baud rate time constant 00h xx xx 00h 00h 00h 00h xx xx xx 00h xx 00h 00h Clock status - Interrupt Pending Bits Reserved - do not write Reserved - do not write Receive Buffer Command register Tx/Rx Interrupt & data transfer mode Extended Features Control Receive Parameter and Control Tx/Rx miscellaneous parameters & mode Tx parameter and control Reserved - do not write Reserved - do not write Transmit Data Buffer Master Interrupt control Miscellaneous Tx/Rx control register Clock Mode Control Lower Byte of Baud rate time constant Upper Byte of Baud rate time constant Miscellaneous Control bits External / Status interrupt control Reserved - do not write Reserved - do not write Tx/Rx buffer and external status Receive condition status - 00h xx xx 00h 00h 00h 00h xx xx xx 00h xx 00h 00h xx f8h 00h 00h 1999 Sep 24 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 MMR Name UART1 Write Register 14 UART1 Write Register 15 Reserved - do not write Reserved - do not write UART1 Read Register 0 UART1 Read Register 1 Reserved - do not write UART1 Read Register 3 Reserved - do not write Reserved - do not write UART1 Read Register 8 Reserved - do not write UART1 Read Register 10 Reserved - do not write Read/Write or Read Only R/W R/W Size 8 8 8 8 Address Offset 85Ch 85Eh 868h 86Ah 860h 862h 864h 866 86Ch 86Eh 870h 872h 874h 876-87Eh Description Miscellaneous Control bits External / Status interrupt control Reserved - do not write Reserved - do not write Tx/Rx buffer and external status Receive condition status Interrupt Pending Bits Reserved - do not write Reserved - do not write Receive Buffer Clock status Reset Value xx f8h 00h 00h RO RO RO 8 8 8 8 8 RO RO 8 8 UART2 Registers UART2 Write Register 0 UART2 Write Register 1 UART2 Write Register 2 UART2 Write Register 3 UART2 Write Register 4 UART2 Write Register 5 Reserved - do not write Reserved - do not write UART2 Write Register 8 UART2 Write Register 9 UART2 Write Register 10 UART2 Write Register 11 UART2 Write Register 12 UART2 Write Register 13 UART2 Write Register 14 UART2 Write Register 15 Reserved - do not write Reserved - do not write UART2 Read Register 0 UART2 Read Register 1 Reserved - do not write UART2 Read Register 3 Reserved - do not write Reserved - do not write UART2 Read Register 8 Reserved - do not write UART2 Read Register 10 Reserved - do not write RO 8 RO RO 8 8 8 8 RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 880h 882h 884h 886h 888h 88Ah 88Ch 88Eh 890h 892h 894h 896h 898h 89Ah 89Ch 89Eh 8A8h 8AAh 8A0h 8A2h 8A4h 8A6h 8ACh 8AEh 8B0h 8B2h 8B4h 8B6-8BEh Clock status Interrupt Pending Bits Reserved - do not write Reserved - do not write Receive Buffer Command register Tx/Rx Interrupt & data transfer mode Extended Features Control Receive Parameter and Control Tx/Rx miscellaneous parameters & mode Tx. parameter and control Reserved - do not write Reserved - do not write Transmit Data Buffer Master Interrupt control Miscellaneous Tx/Rx control register Clock Mode Control Lower Byte of Baud rate time constant Upper Byte of Baud rate time constant Miscellaneous Control bits External / Status interrupt control Reserved - do not write Reserved - do not write Tx/Rx buffer and external status Receive condition status 00h xx xx 00h 00h 00h 00h xx xx xx 00h xx 00h 00h xx f8h 00h 00h 1999 Sep 24 13 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 MMR Name Read/Write or Read Only Size Address Offset Description Reset Value UART3 Registers UART3 Write Register 0 UART3 Write Register 1 UART3 Write Register 2 UART3 Write Register 3 UART3 Write Register 4 UART3 Write Register 5 Reserved - do not write Reserved - do not write UART3 Write Register 8 UART3 Write Register 9 UART3 Write Register 10 UART3 Write Register 11 UART3 Write Register 12 UART3 Write Register 13 UART3 Write Register 14 UART3 Write Register 15 Reserved - do not write Reserved - do not write UART3 Read Register 0 UART3 Read Register 1 Reserved - do not write UART3 Read Register 3 Reserved - do not write Reserved - do not write UART3 Read Register 8 Reserved - do not write UART3 Read Register 10 Reserved - do not write RO 8 RO RO 8 8 8 8 RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8C0h 8C2h 8C4h 8C6h 8C8h 8CAh 8CCh 8CEh 8D0h 8D2h 8D4h 8D6h 8D8h 8DAh 8DCh 8DEh 8E8h 8EAh 8E0h 8E2h 8E4h 8E6h 8ECh 8EEh 8F0h 8F2h 8F4h 8F6-8FEh Rx DMA Registers DMA Control Register Ch.0 Rx FIFO Control & Status Reg Ch.0 Rx Segment Register Ch.0 Rx Buffer Base Register Ch.0 Rx Buffer Bound Register Ch.0 Rx Address Pointer Reg Ch.0 Rx Byte Count Register Ch.0 Rx Data FIFO Register Ch.0 Lo Rx Data FIFO Register Ch.0 Hi Rx DMA Control Register Ch.1 Rx FIFO Control & Status Register Ch.1 Rx Segment Register Ch. 1 Rx 1999 Sep 24 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 16 16 16 16 16 8 8 8 14 100h 101h 102h 104h 106h 108h 10Ah 10Ch 10Eh 110h 111h 112h Control Register Control & Status Register Points to 64 k data segment Wrap Reload Value for A15 - A8, A7 - A0 reloaded to zero by hardware Upper Bound (plus 1) on A15 - A0 Current Address pointer A15 - A0 Corresponds to A15 - A0 Byte Count, generates interrupt if enabled and byte count exceeded. 10Ch = Byte 0 = older, 10Dh = Byte 1 = younger 10Eh = Byte 2 = older, 10Fh = Byte 3 = younger Control Register Control & Status Register Points to 64 k data segment 00h 00h 00h 00h 0000h 0000h 0000h 00h 00h 00h 00h 00h 00h 00h Clock status Interrupt Pending Bits Reserved - do not write Reserved - do not write Receive Buffer - Command register Tx/Rx Interrupt & data transfer mode Extended Features Control Receive Parameter and Control Tx/Rx miscellaneous parameters & mode Tx. parameter and control Reserved - do not write Reserved - do not write Transmit Data Buffer Master Interrupt control Miscellaneous Tx/Rx control register Clock Mode Control Lower Byte of Baud rate time constant Upper Byte of Baud rate time constant Miscellaneous Control bits External / Status interrupt control Reserved - do not write Reserved - do not write Tx/Rx buffer and external status Receive condition status 00h xx xx 00h 00h 00h 00h xx xx xx 00h xx 00h 00h xx f8h 00h 00h Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 MMR Name Buffer Base Register Ch. 1 Rx Buffer Bound Register Ch.1 Rx Address Pointer Reg Ch.1 Rx Byte Count Register Ch.1 Rx Data FIFO Register Ch.1 Lo Rx Data FIFO Register Ch.1 Hi Rx DMA Control Register Ch.2 Rx FIFO Control & Status Register Ch.2 Rx Segment Register Ch. 2 Rx Buffer Base Register Ch. 2 Rx Buffer Bound Register Ch.2 Rx Address Pointer Reg Ch.2 Rx Byte Count Register Ch.2 Rx Data FIFO Register Ch.2 Lo Rx Data FIFO Register Ch.2 Hi Rx DMA Control Register Ch.3 Rx FIFO Control & Status Register Ch.3 Rx Segment Register Ch. 3 Rx Buffer Base Register Ch. 3 Rx Buffer Bound Register Ch.3 Rx Address Pointer Reg Ch.3 Rx Byte Count Register Ch.3 Rx Data FIFO Register Ch.3 Lo Rx Data FIFO Register Ch.3 Hi Rx Read/Write or Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Size 8 16 16 16 16 16 8 8 8 8 16 16 16 16 16 8 8 8 8 16 16 16 16 16 Address Offset 114h 116h 118h 11Ah 11Ch 11Eh 120h 121h 122h 124h 126h 128h 12Ah 12Ch 12Eh 130h 131h 132h 134h 136h 138h 13Ah 13Ch 13Eh Description Wrap Reload Value for A15 - A8, A7 - A0 reloaded to zero by hardware Upper Bound (plus 1) on A15 - A0 Current Address pointer A15 - A0 Corresponds to A15 - A0 Byte Count, generates interrupt if enabled and byte count exceeded. 11Ch = Byte 0 = older, 11Dh = Byte 1 = younger 11Eh = Byte 2 = older, 11Fh = Byte 3 = younger Control Register Control & Status Register Points to 64 k data segment Wrap Reload Value for A15 - A8, A7 - A0 reloaded to zero by hardware Upper Bound (plus 1) on A15 - A0 Current Address pointer A15 - A0 Corresponds to A15 - A0 Byte Count, generates interrupt if enabled and byte count exceeded. 12Ch = Byte 0 = older, 12Dh = Byte 1 = younger 12Eh = Byte 2 = older, 12Fh = Byte 3 = younger Control Register Control & Status Register Points to 64 k data segment Wrap Reload Value for A15 - A8, A7 - A0 reloaded to zero by hardware Upper Bound (plus 1) on A15 - A0 Current Address pointer A15 - A0 Corresponds to A15 - A0 Byte Count, generates interrupt if enabled and byte count exceeded. 13Ch = Byte 0 = older, 13Dh = Byte 1 = younger 13Eh = Byte 2 = older, 13Fh = Byte 3 = younger Reset Value 00h 0000h 0000h 0000h 00h 00h 00h 00h 00h 00h 00h 00h 0000h 0000h 0000h 00h 00h 00h 00h 00h 00h 00h 00h 0000h 0000h 0000h 00h 00h 00h 00h Tx DMA Registers DMA Control Register Ch.0 Tx FIFO Control & Status Register Ch.0 Tx Segment Register Ch. 0 Tx Buffer Base Register Ch. 0 Tx Buffer Bound Register Ch.0 Tx Address Pointer Reg Ch.0 Tx Byte Count Register Ch.0 Tx Data FIFO Register Ch.0 Tx R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 16 16 16 16 140h 141h 142h 144h 146h 148h 14Ah 14Ch Control Register Control & Status Register Points to 64 k data segment Wrap Reload Value for A15 - A8, A7 - A0 reloaded to zero by hardware Upper Bound (plus 1) on A15 - A0 Current Address pointer A15 - A0 Corresponds to A15 - A0 Byte Count, generates interrupt if enabled and byte count exceeded. 14C = Byte0 = older 14D = Byte 1 = younger 00h 00h 00h 00h 0000h 0000h 0000h 0000h 1999 Sep 24 15 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 MMR Name Data FIFO Register Ch.0 Tx DMA Control Register Ch.1 Tx FIFO Control & Status Register Ch.1 Tx Segment Register Ch.1 Tx Buffer Base Register Ch.1 Tx Buffer Bound Register Ch.1 Tx Address Pointer Reg Ch.1 Tx Byte Count Register Ch.1 Tx Data FIFO Register Ch.1 Lo Tx Data FIFO Register Ch.1 Hi Tx DMA Control Register Ch.2 Tx FIFO Control & Status Register Ch.2 Tx Segment Register Ch.2 Tx Buffer Base Register Ch.2 Tx Buffer Bound Register Ch.2 Tx Address Pointer Reg Ch.2 Tx Byte Count Register Ch.2 Tx Data FIFO Register Ch.2 Lo Tx Data FIFO Register Ch.2 Hi Tx DMA Control Register Ch.3 Tx FIFO Control & Status Register Ch.3 Tx Segment Register Ch. 3 Tx Buffer Base Register Ch. 3 Tx Buffer Bound Register Ch.3 Tx Address Pointer Reg Ch.3 Tx Byte Count Register Ch.3 Tx Data FIFO Register Ch.3Lo Tx Data FIFO Register Ch.3 Hi Tx Read/Write or Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Size 16 8 8 8 8 16 16 16 16 16 8 8 8 8 16 16 16 16 16 8 8 8 8 16 16 16 16 16 Address Offset 14Eh 150h 151h 152h 154h 156h 158h 15Ah 15Ch 15Eh 160h 161h 162h 164h 166h 168h 16Ah 16Ch 16Eh 170h 171h 172h 174h 176h 178h 17Ah 17Ch 17Eh 180-1FEh Description 14E = Byte2 = older 14F = Byte3 = younger Control Register Control & Status Register Points to 64 k data segment Wrap Reload Value for A15 - A8, A7 - A0 reloaded to zero by hardware Upper Bound (plus 1) on A15 - A0 Current Address pointer A15 - A0 Corresponds to A15 - A0 Byte Count, generates interrupt if enabled and byte count exceeded. Byte0 & 1 Byte2 & 3 Control Register Control & Status Register Points to 64 k data segment Wrap Reload Value for A15 - A8, A7 - A0 reloaded to zero by hardware Upper Bound (plus 1) on A15 - A0 Current Address pointer A15 - A0 Corresponds to A15 - A0 Byte Count, generates interrupt if enabled and byte count exceeded. Byte0 & 1 Byte2 & 3 Control Register Control & Status Register Points to 64 k data segment Wrap Reload Value for A15 - A8, A7 - A0 reloaded to zero by hardware Upper Bound (plus 1) on A15 - A0 Current Address pointer A15 - A0 Corresponds to A15 - A0 Byte Count, generates interrupt if enabled and byte count exceeded. Byte0 & 1 Byte2 & 3 RESERVED for future DMA Reset Value 0000h 00h 00h 00h 00h 0000h 0000h 0000h 0000h 0000h 00h 00h 00h 00h 0000h 0000h 0000h 0000h 0000h 00h 00h 00h 00h 0000h 0000h 0000h 0000h 0000h - Miscellaneous DMA Registers Rx Character Time Out Register Ch.0 Rx Character Time Out Register Ch.1 Rx Character Time Out Register Ch.2 Rx Character Time Out Register Ch.3 Global DMA Interrupt Register GPOut R/W R/W R/W R/W R/W R/W 8 8 8 8 16 8 200h 202h 204h 206h 210h 260h 0 value disables counter interrupt. Same as above, for Rx1 Same as above, for Rx2 Same as above, for Rx3 DMA Interrupt Flags GPOut[7] drives pin 98 (GPOut) through an inverter. GPOut[6-0] are unused, and must be written with zeroes. 00h 00h 00h 00h 0000h 8xh 1999 Sep 24 16 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 MMR Name Read/Write or Read Only Size Address Offset Description Reset Value Memory Interface (MIF) Registers B0CFG B0AM B0TMG B1CFG B1AM B1TMG B2CFG B2AM B2TMG B3CFG B3AM B3TMG B4CFG B4AM B4TMG B5CFG B5AM B5TMG MBCL Reserved - do not write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 280h 281h 282h 284h 285h 286h 288h 289h 28Ah 28Ch 28Dh 28Eh 290h 291h 292h 294h 295h 296h 2BEh 2BFh MIF Bank 0 Config MIF Bank 0 Base Address MIF Bank 0 Timing Params MIF Bank 1 Config MIF Bank 1 Base Address MIF Bank 1 Timing Params MIF Bank 2 Config MIF Bank 2 Base Address MIF Bank 2 Timing Params MIF Bank 3 Config MIF Bank 3 Base Address MIF Bank 3 Timing Params MIF Bank 4 Config MIF Bank 4 Base Address MIF Bank 4 Timing Params MIF Bank 5 Config MIF Bank 5 Base Address MIF Bank 5 Timing Params MIF Memory Bank Configuration Lock Register Reserved - do not write 0Fh 00h Miscellaneous Registers Hi-Pri Soft Ints & Pin Mux Control Reg. XInt2 R/W R/W 16 8 2D0h 2D2h Control bits for Hi-Priority Soft Ints, and Pin Mux External Interrupt 2 Control 0000h 00h FUNCTIONAL DESCRIPTION The XA-H3 functions are described in the following sections. Because all blocks are thoroughly documented in either the IC25 XA Data Handbook, or the XA-H3 User Manual, only brief descriptions are given in this datasheet, in conjunction with references to the appropriate document. XA CPU XA CPU The CPU is a 30 MHz implementation of the standard XA CPU core. See the XA Data Handbook (IC25) for details. The CPU core is identical to the G3 core. See caveat in next paragraph about the Bus Interface Unit. BIU Internal Cpu Bus Bus Interface Unit (BIU) This is the internal Bus, not the bus at the pins. This internal bus connects the CPU to Memory Controller. WARNING: Immediately after reset, always write BTRH = 51h, followed by BTRL = 40h, in that order. Once written, do not change the values in these registers. Follow these two writes with five NOPS. Never write to the BCR register, it comes out of reset initialized to 07h, which is the only value that will work. External Memory and I/O Bus Memory Controller DMA Channels x8 SU01236 Figure 1. XA CPU Core BIU (Bus Interface Unit) 1999 Sep 24 17 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 Timers 0 and 1 Timers 0 and 1 are the standard XA-G3 timer 0 and 1. Each has an associated I/O pin and interrupt. See the XA-G3 data sheet in the IC25 XA Data Handbook for details. Many XA derivatives include a standard XA Timer 2. The Timer 2 block has been removed in order to provide other functions on the XA-H3. ResetOut The P3.2_Timer0_ResetOut pin provides an external indication (if the ResetOut function is enabled in the RSRSRC register) via an active low output when an internal reset occurs (internal reset is Reset instruction or Watchdog time out.) If the ResetOut function is enabled, the ResetOut pin will be driven low when a Watchdog reset occurs or the Reset instruction is executed. This signal may be used to inform other devices in the system that the XA-H3 has been internally reset. The ResetIn signal does NOT get passed on to ResetOut. When activated, the duration of the ResetOut pulse is 256 system clocks. WARNING: At power on time, from the time that power coming up is valid, the P3.2_Timer0_ResetOut pin may be driven low for any period from zero nanoseconds up to 258 system clocks. This is true independently of whether ResetIn is active or not. Watchdog Timer This timer is a standard XA-G3 Watchdog Timer. See the G3 datasheet in IC25. Also, if you intend to use the Watchdog Timer to assert the ResetOut pin, see "ResetOut" in the XA-H3 User Manual. The Watchdog Timer is enabled at reset, and must be periodically fed to prevent timeout. If the watchdog times out, it will generate an internal reset; and if ResetOut is enabled the internal reset will generate a ResetOut pulse (active low pulse on ResetOut pin.) Reset On the XA-H3 there are two pins associated with reset. The ResetIn pin provides an external reset into the XA-H3. The port pin P3.2_Timer0_ResetOut output can be configured as ResetOut. Because ResetOut does not reflect ResetIn, the ResetOut pin can be tied directly back into the ResetIn pin without other PC board logic. This configuration will make all resets (internal or external) appear to the XA as external resets. See the XA-H3 User Manual for a full discussion of the reset functions. Reset Source Register The reset source identification register (RSTSRC) indicates the cause of the most recent XA reset. The cause may have been an externally applied reset signal, execution of the RESET instruction, or a Watchdog reset. Figure 2 shows the fields in the RSTSRC register. If the ResetOut function is tied back into the ResetIn pin, then all resets will be external resets, and will thus appear as external resets in the reset source register. RSTSRC[7] enables the ResetOut function; 1 = Enabled, 0 = Disabled. See XA-H3 User Manual for details; RSTSRC[7] differs in function from most other XA derivatives. ResetIn The ResetIn function is the standard XA-G3 ResetIn function. The ResetIn signal does NOT get passed on to ResetOut. See the XA-H3 User Manual for details on reset. RSTSRC Reg Type and Address = SFR 463h Not Bit Addressable Reset Value = see below MSB ROEN -- -- -- -- R_WD R_CMD LSB R_EXT BIT RSTSRC.7 RSTSRC.6 RSTSRC.5 RSTSRC.4 RSTSRC.3 RSTSRC.2 RSTSRC.1 RSTSRC.0 SYMBOL ROEN - - - - R_WD R_CMD R_EXT FUNCTION ResetOut function enable bit - see XA-H3 User Manual for details Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Indicates that the last reset was caused by a watchdog timer overflow (see WARNING.) Indicates that the last reset was caused by execution of the RESET instruction (see WARNING.) Indicates that the last reset was caused by the external ResetIn input. WARNING: If ResetOut function is tied back into ResetIn pin, RSTSRC will always show external reset ONLY, because external reset always takes precedence over internal reset. SU01237 Figure 2. RSTSRC Reset Source Register MEMORY CONTROLLER AND I/O BUS INTERFACE The Memory Controller and bus interface generate bus cycles that are designed to service SRAMs, Flash, EEPROM, peripheral chips, etc. The XA-H3 has a highly programmable memory bus interface. Most SRAMs, Flash, ROMs, and peripheral chips can be connected to this interface with no external decode logic or interface chips. The bus interface provides 6 mappable chip select outputs. The bus timing for each individual memory bank or peripheral can be programmed to accommodate slow or fast devices, with various bus protocols. 1999 Sep 24 18 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 Each memory bank and associated chip select is capable of supporting a 1 MB address space (six chip selects can thus support 6 MB of SRAM and other generic devices.) The Memory Interface can be programmed to support both Intel style and 68000 bus style SRAMs and peripherals. XA-H3 Memory Controller CS5 (or P3.1, RTS1) CS4 (or P3.0, RTClk1) CS3 CS2 CS1 CS0 A19-A0 D15-D0 SRAM Controller Dynamic Bus Sizing Dynamic Bus Timing ClkOut BHE BLE OE WE WAIT, SIZE16 SU01238 Figure 3. Memory Bus Interface Signal Pins Bus Interface Pins For the following discussion, see Figure 3. Chip Select Pins There are six chip select pins (CS5 - CS0)mapped to six sets of bank control registers. The following attributes are individually programmable for each bank and associated chip select : bank on/off, address range, external device access time, detailed bus strobe sequence, and bus width. WARNING: On the external bus, ALL XA-H3 reads are 16-bit Reads. If the CPU instruction only specifies 8-bits, then the CPU uses the appropriate byte, and discards the extra byte. Thus "8-Bit Reads" and "16-Bit Reads" appear to be identical on the bus. On an 8-bit bus, this will appear as two consecutive 8-bit reads even though the CPU instruction specified a byte read. Some 8-bit I/O devices (especially FIFOs) cannot operate correctly with 2 bytes being Read for a 1 Byte Read. The most common (and least expensive) solution is to operate these 8-bit devices on a 16-bit bus, and access them in software on all odd byte (or all even byte) boundaries. An added benefit of this technique is that byte reads are faster than on an 8-bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes. Clock Output The CLKOUT pin allows easier external bus interfacing in some situations. This output reflects the XTALIn clock input to the XA (referred to internally as CClk or System Clock), but is delayed to match the external bus outputs and strobes. The default is for CLKOUT to be output enabled at reset, but it may be turned off (tri-state disabled) by software via the MICFG MMR. WARNING: The capacitive loading on this output must not exceed 40 pf. 1999 Sep 24 19 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 CS5 I/O Chip or Memory CS4 I/O Chip or Memory CS3 I/O Chip or Memory CS2 I/O Chip or Memory XA-H3 CS0 OE A19-A0 D15-D0 CS1 BLE BHE A15-A1 D15-D0 CS BLE BHE A15-A1 D15-D0 OE WE 32 k x 16 SRAM CS WE A16-A0 D7-D0 OE A16-A0 D7-D0 ROM or Flash 128 k x 8 WE NOTE: The 16-bit wide RAM does not need the A0 pin from the processor. During byte writes to the RAM, the A0 value will cause either BLE or BHE pin to go active from the XA-H3, but not to both. For all Word Writes, Word Reads, Code Fetches, and Byte Reads, both BLE and BHE will go active. SU01239 Figure 4. Typical System Bus Configuration 1999 Sep 24 20 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 Table 4. Memory interface control registers Register Name MRBH "MMR Base Address" High Reg Type SFR 8 bits SFR 8 bits MMR 8 bits MMR 8 bits MMR 8 bits MMR 8 bits MMR 8 bits Description This SFR is used to relocate the MMRs. It contains address bits a23 - a16 of the base address for the 4 kB Memory Mapped Register space. See the User Manual for using this SFR to relocate the MMRs. Contains address bits a15 - a12 of the base address for the 4 kB Memory Mapped Register space. Contains the CLKOUT Enable bit. Contains the bits for locking and unlocking the BiCFG Registers. Contains the size, type, bus width, and enable bits for Memory Bank i. Contains the base address bits for Memory Bank i. Contains the timing control bits for Memory Bank i. MRBL MICFG MBCL BiCFG BiAM BiTMG "MMR Base Address" Low MIF Configuration Memory Bank Configuration Lock Bank i Configuration Bank i Base Address Bank i Timing EIGHT CHANNEL DMA CONTROLLER The XA-H3/H4 has eight DMA channels; one Rx DMA channel dedicated to each UART Receive (Rx) channel, and one Tx DMA channel dedicated to each UART Transmit (Tx) channel. All DMA channels are optimized to support memory efficient circular data buffers in external memory. All DMA channels can also support traditional linear data buffers. Transmit DMA Channel Modes The four Tx channels have three DMA modes specifically designed for various applications of the attached UARTs. These modes are summarized in the following table. Full details for all DMA functions can be found in the DMA chapter of the XA-H3 User Manual. Table 5. Tx DMA modes summary Mode Tx Chaining Byte Count Source Header in memory Maskable Interrupt On stop Description DMA channel picks up header from memory at end of transmission. If byte count in header is greater than zero, then DMA transmits the number of bytes specified in the byte count. If byte count equals 0, then a maskable interrupt is generated. This process repeats until byte count in data header is zero. See XA-H3 User Manual for details. Processor loads byte count into DMA. DMA sends that number of bytes, generates maskable interrupt, and stops. DMA runs until commanded to stop by processor. CPU loaded value in Byte Count Register is used to generate an interrupt for every n bytes. Every time byte counter rolls over, a new maskable interrupt is generated. Stop on TC Periodic Interrupt Processor loads Byte Count Register Loaded by processor into DMA, used by DMA only to determine the number of bytes between interrupts. Processor can calculate the byte count from the DMA address pointer. Byte count completed (Tx DMA stops) When Byte Counter reaches zero and is reloaded by DMA hardware from the byte count register. Receive DMA Channel Modes The Rx DMA channels have two DMA modes specifically designed for various applications of the attached UARTs. These modes are summarized in the following table. For full details on implementation and use, see the XA-H3 User Manual. 1999 Sep 24 21 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 Table 6. Rx DMA modes summary Mode Periodic Interrupt Byte Count Source Loaded by processor into DMA, used by DMA only to determine the number of bytes between interrupts. Processor can calculate the byte count from the DMA address pointer. Byte Count can be calculated by software from the DMA address pointer. Maskable Interrupt When Byte Counter reaches zero and is reloaded by DMA hardware from the byte count register. Description The DMA channel runs until commanded to stop by the processor. It generates a maskable interrupt once per n bytes, where n is the number written once into the byte count register by the processor, thus an interrupt is generated once every n received bytes. Processor specifies time out period between incoming characters. If no character is received within that time, a maskable interrupt is generated. Whenever a new character is received, it is moved into the memory buffer - no interrupt is generated. Asynchronous with Character Time Out Asynchronous without interrupt If no character is received within a specified time out period, then interrupt. No interrupt generated Byte Count can be calculated by software from the DMA address pointer. Data FIFO 3 Data FIFO 1 Data FIFO 2 Data FIFO 0 DMA Control Segment Buffer Base Buffer Bound Address Pointer Byte Count FIFO Control Rx Channel Rx Time Out Data FIFO 3 Data FIFO 1 Data FIFO 2 Data FIFO 0 DMA Control Segment Buffer Base Tx Channel Buffer Bound Address Pointer Byte Count FIFO Control SU01240 Figure 5. Rx and Tx DMA Registers DMA Registers In addition to the 16-bit Global DMA Interrupt Register (which is shared by all eight DMA channels), each DMA channel has seven control registers and a four-byte Data FIFO. The four Rx DMA channels have one additional register, the Rx Character Time Out Register. All DMA registers can be read and written in Memory Mapped Register (MMR) space. These registers are summarized below. * Global DMA Interrupt Register (not shown in figure): All DMA interrupt flags are in this register . * DMA Control Register: Contains the master mode select and interrupt enable bits for the channel. 1999 Sep 24 22 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 * Segment Register: Holds A23-A16 (the current segment) of the 24-bit data buffer address. * Buffer Base Register: Holds a pointer (A15-A8) to the lowest byte in the memory buffer. Hi-Z, and allows the pin to be used as an input. WARNING: At power on time, from the time that power coming up is valid, the P3.2_Timer0_ResetOut pin may be driven low for any period from zero nanoseconds up to 258 system clocks. This is true independently of whether ResetIn is active or not. * Buffer Bound Register: Points to the first out-of-bounds address above a circular buffer. Power Reduction Modes The XA-H3 supports Idle and Power Down modes of power reduction. The idle mode leaves most peripherals running in order to allow them to activate the processor when an interrupt is generated. The power down mode stops the oscillator in order to absolutely minimize power. The processor can be made to exit power down mode via a reset or one of the external interrupt inputs (INT0 or INT1). This will occur if the interrupt is enabled and its priority is higher than that defined by IM3 through IM0. In power down mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM. This retains the RAM, register, and SFR contents at the point where power down mode was entered. WARNING: VDD must be raised to within the operating range before power down mode is exited. * Address Pointer Register: Points to a single byte or word in the data buffer in memory. The 24-bit DMA address is formed by concatenating the contents of the Segment Register [A23-A16] with the contents of the Address Pointer Register [A15-A0]. * Byte Count Register: Holds the initial number of bytes to be transferred. In Tx Chaining mode, this register is not used because the byte count is brought into the byte counter from buffer headers in memory. * FIFO Control & Status Register: Holds the queuing order and full/empty status for the Data FIFO Registers. * Data FIFO Registers: A four-byte data FIFO buffer internal to the DMA channel. Interrupts In the XA architecture, all exceptions, including Reset, are handled in the same general exception structure. The highest priority exception is of course Reset, and it is non-maskable. All exceptions are vectored through the Exception Vector Table in low memory. Coming out of Reset, these vectors must be stored in non-volatile memory based at location 000000. Later in the boot sequence, SRAM or other memory can be mapped into this address space if desired. There is a feature in the XA-H3 Memory Controller called "Bank Swap" that supports replacing the ROM vector table and other low memory with RAM. See the XA-H3 User Manual for details. The XA-H3 has a standard XA CPU Interrupt Controller, implemented with 15 Maskable Event Interrupts. Event Interrupts are defined as maskable interrupts usually generated by hardware events. However, in the XA-H3, 4 of the 15 Event Interrupts are generated by software writing directly to the interrupt flag bit. These 4 interrupts are referred to as High Priority Software Interrupts. See the IC25 XA Data Handbook for a full explanation of the exception structure, including event interrupts, of the XA CPU. Because the High Priority Software Interrupts are specific to the XA-H3, they are explained in the XA-H3 User Manual. * Rx Char Time Out Register (RxCTOR, Rx DMA channels only): Holds the initial value for an 8-bit character timeout countdown timer which can generate an interrupt. Four UARTS * Asynchronous transfers up to 230.4 kbps * 5, 6, 7, or 8 data bits per character * 1, 1.5, or 2 Stop bits per character * Even or Odd parity generate and check * Parity, Rx Overrun, and Framing Error detection * Break detection * Programmable Baud Rate Generator * Auto Echo and Loopback Modes I/O Port Output Configuration Port input/output configurations are the same as standard XA ports: open drain, quasi-bidirectional, push-pull, and off (off means tri-state 1999 Sep 24 23 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 XA Core Interrupt Controller DMAH DMA Interrupts DMAL RxD0 CTS0 CD0 RxD1 CTS1 CD1_INT2 UART0/ UART1 INT2 RxD2 CTS2 CD2 RxD3 CTS3 CD3 INT0 INT1 Timer 0 UART2/ UART3 Interrupt Enable/ Disable Bits Master Enable "EA" Interrupt To XA CPU Timer 1 High Priority Software Ints HSWR 3-0 4 SU01241 Figure 6. XA-H3 Interrupt Structure Overview 1999 Sep 24 24 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 Table 7. UART0 Interrupts (Interrupt structure is the same except for bit locations for all 4 UARTs) Potential UART0 Interrupt Rx Character Available Individual Enable Bit MMR Hex Offset - Source Bit MMR Hex Offset RR0[0] 820[0] Group Enable Bit(S) MMR Hex Offset WR1[4:3] 802[4:3] Group Flag Bit MMR Hex Offset Even Channel Rx IP RR3[5] 826[5] Master Enable Bit MMR Hex Offset UART0/1 Master Interrupt Enable WR9[3] 812[3] CRC/Framing Error Rx Overrun Parity Error Tx Buffer Empty - - WR1[2] 802[2] See WR1[1] RR1[6] 822[6] RR1[5] 822[5] RR1[4] 822[4] RR0[2] 820[2] Break/Abort Break/ Abort IE WR15[7] 81E[7] Tx Underrun/EOM Tx Underrun/EOM IE WR15[6] 81E[6] CTS CTS IE WR15[5] 81E[5] DCD DCD IE WR15[3] 81E[3] Zero Count Zero Count IE WR15[1] 81E[1] RR0[1] 820[1] RR0[3] 820[3] RR0[5] 820[5] RR0[6] 820[6] RR0[7] 820[7] Tx Interrupt Enable WR1[1] 802[1] Master External/Status Interrupt Enable WR1[0] 802[0] Even Channel Tx IP RR3[4] 826[4] Even Channel External/Status IP RR3[3] 826[3] EXCEPTION/TRAPS PRECEDENCE Description Reset (h/w, watchdog, s/w) Break Point Trace Stack Overflow Divide by 0 User RETI TRAP 0-15 (software) Vector Address 0000-0003 0004-0007 0008-000B 000C-000F 0010-0013 0014-0017 0040-007F Arbitration Ranking 0 (High) 1 1 1 1 1 1 1999 Sep 24 25 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 EVENT INTERRUPTS Description Event Interrupt Source High Priority Software Interrupt 3 High Priority Software Interrupt 2 High Priority Software Interrupt 1 High Priority Software Interrupt 0 UART "UART2/3" Interrupt UART "UART0/1" Interrupt DMA "DMAH" Interrupt DMA "DMAL" Interrupt External Interrupt 2 (INT2) Timer 1 Flag Bit HSWR3 MMR 2D0[15] HSWR2 MMR 2D0[14] HSWR1 MMR 2D0[13] HSWR0 MMR 2D0[12] multiple OR from UART2 & UART3 multiple OR from UART0 & UART1 multiple OR from DMA multiple OR from DMA IE2 MMR 2D2[0] TF1 SFR 410[7] 287 IE1 SFR 410[3] 283 TF0 SFR 410[5] 285 IE0 SFR 410[1] Interrupt Vector Address 00BF-00BC Enable Bit (SFR) EHSWR3 427[7] 33F EHSWR2 427[6] 33E EHSWR1 427[5] 33D EHSWR0 427[4] 33C ESC23 427[1] 339 ESC01 427[0] 338 EDMAH 426[6] 336 EDMAL 426[5] 335 EX2 426[4] 334 ET1 426[3] 333 EX1 426[2] 332 ET0 426[1] 331 EX0 426[0] 330 Priority Register Bit Field (SFR) PHSWR3 4A7[6:4] PHSWR2 4A7[2:0] PHSWR1 4A6[6:4] PHSWR0 4A6[2:0] PSC23 4A4[6:4] PSC01 4A4[2:0] PDMAH 4A3[2:0] PDMAL 4A2[6:4] PX2 4A2[2:0] PT1 4A1[6:4] PX1 4A1[2:0] PT0 4A0[6:4] PX0 4A0[2:0] 17 Arb. Rank 00BB-00B8 16 00B7-00B4 15 00B3-00B0 14 00A7-00A4 11 00A3-00A0 10 009B-0098 8 0097-0094 7 0093-0090 6 008F-008C 5 External Interrupt 1 (INT1) Timer 0 008B-0088 4 0087-0084 3 External Interrupt 0 (INT0) 0083-0080 2 SOFTWARE INTERRUPTS Description Software Interrupt 1 Software Interrupt 2 Software Interrupt 3 Software Interrupt 4 Software Interrupt 5 Software Interrupt 6 Software Interrupt 7 Flag Bit SWR1 SWR2 SWR3 SWR4 SWR5 SWR6 SWR7 Vector Address 0100-0103 0104-0107 0108-010B 010C-010F 0110-0113 0114-0117 0118-011B Enable Bit SWE1 SWE2 SWE3 SWE4 SWE5 SWE6 SWE7 Interrupt Priority (fixed at 1) (fixed at 2) (fixed at 3) (fixed at 4) (fixed at 5) (fixed at 6) (fixed at 7) 1999 Sep 24 26 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 ABSOLUTE MAXIMUM RATINGS Parameter Operating temperature under bias Storage temperature range Voltage on any other pin to VSS Maximum IOL per I/O pin Power dissipation (based on package heat transfer, not device power consumption) Rating -55 to +125 -65 to +150 -0.5 to VDD+0.5 V 15 1.5 Unit C C v mA W PRELIMINARY DC ELECTRICAL CHARACTERISTICS VDD = 5.0 V +/- 10% or 3.3 V +/- 10% unless otherwise specified; Tamb = -40C to +85C for industrial, unless otherwise specified. Symbol IDD IID IPDI VRAM VIL VIH VIH1 VOL VOH1 VOH2 CIO IIL ILI ITL Parameter Power supply current, operating Power supply current, Idle mode Power supply current, Power Down mode1 RAM keep-alive voltage Input low voltage Input high voltage, except Xtal1, RST Input high voltage to Xtal1, RST Output low voltage all ports8 Output high voltage, all ports Output high voltage, all ports Input/Output pin capacitance Logical 0 input current, all ports7 Input leakage current, all ports6 Logical 1 to 0 transition current, all ports5 VIN = 0.45 V VIN = VIL or VIH At VDD = 5.5 V At VDD = 3.6 V For both 3.0 & 5.0 V IOL = 3.2 mA, VDD = 4.5 V IOL = 1.0 mA, VDD = 3.0 V IOH = -100 A, VDD = 4.5 V IOH = -30 A, VDD = 3.0 V IOH = 3.2 mA, VDD = 4.5 V IOH = 1.0 mA, VDD = 3.0 V 2.4 2.0 2.4 2.2 15 -50 10 -650 -250 Test Conditions 5.0 V, 30 MHz 3.3 V, 30 MHz 5.0 V, 30 MHz 3.3 V, 30 MHz 5.0 V, 3.0 V 1.5 -0.5 2.2 0.7 VDD 0.5 0.4 0.22 VDD Limits Min Typ 64 55 50 44 Max 80 70 70 60 500 Unit mA mA mA mA A V V V V V V V V V V pF A A A A NOTE: 1. VDD must be raised to within the operating range before power down mode is exited. 2. Ports in quasi-bidirectional mode with weak pullup. 3. Ports in PUSH-PULL mode, both pullup and pulldown assumed to be the same strength. 4. In all output modes. 5. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when VIN is approximately 2 V. 6. Measured with port in high impedance mode. 7. Measured with port in quasi-bidirectional mode. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15 mA (NOTE: This is +85C specification for VDD = 5 V) Maximum IOL per port pin: Maximum IOL per 8-bit port: 26 mA 71 mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 1999 Sep 24 27 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 PRELIMINARY AC ELECTRICAL CHARACTERISTICS (5.0 V +/-10%) Symbol Figure Fig re Parameter All Cycles FC tC tCHCX tCLCX tCLCH tCHCL tAVSL tCHAH tCHAV tCHSH tCHSL tCODH tAHDR 13 13 13 13 13 All All All All All 14 10 System Clock Frequency System Clock Period = 1/FC XTALIN High Time XTALIN Low Time XTALIN Rise Time XTALIN Fall Time Address Valid to Strobe low Address hold after CLKOUT rising edge 7 Delay from CLKOUT rising edge to address valid Delay from CLKOUT rising edge to Strobe High7 Delay from CLKOUT rising edge to Strobe Low7 ClkOut Duty Cycle High (into 40 pF max.) Data Read Only Address hold (A19 - A1 only, not A0) after CS, BLE, BHE rise at end of Data Read Cycle (not code fetch) Data Read and Instruction Fetch Cycles tDIS tDIH tOHDE tCHDV tDVSL tSHAH tSHDH tWS tWH 7, 8, 10, 11 7, 8, 10, 11 10 9 12 9, 12 9, 12 15 15 Data In Valid setup to ClkOut rising edge Data In Valid hold after ClkOut rising edge 2 OE high to XA Data Bus Driver Enable Write Cycles Clock High to Data Valid Data Valid prior to Strobe Low Minimum Address Hold Time after strobe goes inactive Data hold after strobes (CS and BHE/BLE) high Wait Input WAIT setup (stable high or low) to CLKOUT rising edge WAIT hold (stable high or low) after CLKOUT rising edge 20 0 - - ns ns - tC - 23 tC - 25 tC - 25 25 - - - ns ns ns ns 25 0 tC - 14 - - - ns ns ns tC - 12 - ns 0 33.33 tC* 0.5 tC* 0.4 - - tC - 21 1 - 1 1 tCHCX-7 30 - - - 5 5 - - 25 21 19 tCHCX+3 MHz ns ns ns ns ns ns ns ns ns ns ns Limits Min Max Unit NOTE: 1. On a 16-bit bus, if only one byte is being written, then only one of BLE or BHE will go active. On an 8-bit bus, BLE goes active for all (odd or even address) accesses. BHE will not go active during any accesses on an 8 bit bus. 2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all reads and fetches, in order to meet hold time, the slave should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the address changes. 3. To avoid 3-State fights during read cycles and fetch cycles, do not drive data bus until OE goes active 4. WARNING: ClkOut is specified at 40 pF max. More than 40 pf on ClkOut may significantly degrade the ClkOut waveform. Load capacitance for all outputs (except ClkOut) = 80 pF. 5. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-H3 User Manual for details. 6. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16-bit bus, A3 - A1 are incremented for each new word of the burst. On an 8-bit bus, A3 - A0 are incremented for each new byte of the burst code fetch. 7. The MIN value for this parameter is guaranteed by design and is not tested in production to the specified limit. In those cases where a maximum value is specified in the table for this parameter, it is tested. 1999 Sep 24 28 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 AC ELECTRICAL CHARACTERISTICS (3.3 V +/-10%) Vdd = 3.3 V +/- 10%; Tamb = -40C to +85C ( industrial ) Symbol Fig re Figure Parameter All Cycles FC tC tCHCX tCLCX tCLCH tCHCL tAVSL tCHAH tCHAV tCHSH tCHSL tCODH tAHDR 13 13 13 13 13 All All All All All 14 10 System Clock (internally called CClk) Frequency System Clock Period = 1/FC XTALIN High Time XTALIN Low Time XTALIN Rise Time XTALIN Fall Time Address Valid to Strobe low Address hold after CLKOUT rising edge 7 Limits Min 0 33.33 tC* 0.5 tC* 0.4 - - tC - 21 1 - 1 1 tCHCX-7 tC - 12 7 Max 30 - - - 5 5 - - 30 28 25 tCHCX+3 - Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns Delay from CLKOUT rising edge to address valid Delay from CLKOUT rising edge to Strobe High ClkOut Duty Cycle High (into 40 pF max.) Data Read Only Address hold (A19 - A1 only, not A0) after CS, BLE, BHE rise at end of Data Read Cycle (not code fetch) Data Read and Instruction Fetch Cycles Data In Valid setup to ClkOut rising edge Data In Valid hold after ClkOut rising edge 2 OE high to XA Data Bus Driver Enable Write Cycles Clock High to Data Valid Data Valid prior to Strobe Low Minimum Address Hold Time after strobe goes inactive Data hold after strobes (CS and BHE/BLE) high Wait Input WAIT setup (stable high or low)prior to CLKOUT rising edge WAIT hold (stable high or low) after CLKOUT rising edge Delay from CLKOUT rising edge to Strobe Low 7 tDIS tDIH tOHDE tCHDV tDVSL tSHAH tSHDH tWS tWH 7, 8, 10, 11 7, 8, 10, 11 10 9 12 9, 12 9, 12 15 15 32 0 tC - 19 - tC - 23 - - - 30 - - - - - ns ns ns ns ns ns ns ns ns tC - 25 tC - 25 25 0 NOTE: 1. On a 16-bit bus, if only one byte is being written, then only one of BLE or BHE will go active. On an 8-bit bus, BLE goes active for all (odd or even address) accesses. BHE will not go active during any accesses on an 8-bit bus. 2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all reads and fetches, in order to meet hold time, the slave should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the address changes. 3. To avoid 3-State fights during read cycles and fetch cycles, do not drive data bus until OE goes active 4. WARNING: ClkOut is specified at 40 pF max. More than 40 pf on ClkOut may significantly degrade the ClkOut waveform. Load capacitance for all outputs (except ClkOut) = 80 pF. 5. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-H3 User Manual for details. 6. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16-bit bus, A3 - A1 are incremented for each new word of the burst. On an 8-bit bus, A3 - A0 are incremented for each new byte of the burst code fetch. 7. The MIN value for this parameter is guaranteed by design and is not tested in production to the specified limit. In those cases where a maximum value is specified in the table for this parameter, it is tested. 1999 Sep 24 29 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 TIMING DIAGRAMS All references to numbered Notes are to the notes following the AC Electrical Characteristics tables ClkOut A0 tCHAV A19-A1 tCHAH tCHSL CS tAVSL tAHDR (Does Not Include A0) tCHSH BHE/BLE OE Note 3 tDIS tDIH (Note 2) D15-D0 Note: On Generic Data Reads, A0 can terminate a full clock period before A19-A1, and therefore should not be used on some peripheral devices. SU01277 Figure 7. Read on 16-Bit Bus ClkOut tCHAV A[19:0] Address tCHSL CS tAVSL tCHSH tCHAV Address + 2 tCHAV Address + 4 BHE/BLE tOHDE OE Note 3 tDIH Note 2 tDIH Note 2 tDIH (Note 2) Driven by XA tDIS D[15:0] Driven by XA tDIS tDIS Note: The processor can prefetch from one to eight words. SU01131 Figure 8. Burst Code Fetch on 16-Bit Bus 1999 Sep 24 30 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 ClkOut tCHAV A tCHSL CS tAVSL tSHAH tCHSH BHE/BLE Note 1 WE tCHDV tSHDH D SU01278 Figure 9. Write ( byte write on 8-bit bus, or all writes on 16-bit bus ) ClkOut A19 - A1 A0 tCHSL CS tAVSL BLE OE Note 3 tDIS D7 - D0 Driven by XA Note 2 tDIS tDIH Note 2 Driven by XA tOHDE tCHAV tCHSH tAHDR On all cycles on 8-bit bus, BHE remains high (inactive) Note: On the external bus, ALL XA-H4 reads are 16-bit reads. If the CPU instruction only specifies 8-bits, then the CPU uses the appropriate byte, and discards the extra byte. Thus, "8-Bit Reads" and "16-Bit Reads" appear to be identical on the bus. On an 8-bit bus, this will appear as two consecutive 8-bit reads even though the CPU will only use one of the two bytes. WARNING: Some 8-bit I/O devices (especially FIFOS) cannot operate correctly with 2 bytes being read for a one byte read. The most common (and least expensive) solution is to operate these 8-bit devices on a 16-bit bus, and access them in software on all odd byte (or all even byte) boundaries. An added benefit of this technique is that byte reads are faster than on an 8-bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes. SU01283 Figure 10. Read (16-Bit or 8-Bit) on 8 Bit Bus 1999 Sep 24 31 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 Clkout tCHAV tCHAV Even Address tCHAV OE, BLE, CS Note 3 tDIS D[7:0] tDIH Note 2 LS Byte MS Byte tDIS tDIH Note 2 LS Byte tDIS tDIH Note 2 MS Byte tDIS tDIH Note 2 tCHSH Address + 1 tCHAV Address + 2 tCHAV Address + 3 Note: BHE remains high (inactive) for all accesses on an 8-bit bus. A burst code fetch can be from 1 to 8 words (1 word = 2 bytes), a 2 word fetch is shown here. SU01245 Figure 11. Burst Code Fetch on 8-bit bus Clkout tCHAV A19 - A1 tCHSL tCHSH A0 tCHSL CS tAVSL tSHAH tSHAH tAVSL BLE, WE tSHDH tDVSL D7 - D0 Note. OE is inactive during all writes. SU01246 Figure 12. 16-Bit Write on 8-Bit Bus 1999 Sep 24 32 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 VDD - 0.5 0.7 VDD XTALIN 0.45 V 0.2 VDD - 0.1 tCHCX tCHCL tCLCX tC tCLCH SU01146 Figure 13. External Clock Input Drive tCODH ClkOut WARNING: ClkOut is specified into 40 pF max, do not overload. SU01147 Figure 14. ClkOut Duty Cycle ClkOut tWS tWH WAIT tWS - Setup time of WAIT to rising edge of ClkOut. tWH - Hold time of WAIT after ClkOut High. SU01148 Figure 15. External WAIT Pin Timing 1999 Sep 24 33 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 1999 Sep 24 34 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 NOTES 1999 Sep 24 35 Philips Semiconductors Preliminary specification CMOS 16-bit highly integrated microcontroller XA-H3 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 09-99 Document order number: 9397 750 06431 Philips Semiconductors 1999 Sep 24 36 |
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